1. Technical Field
The present invention relates to a semiconductor integrated circuit, and more particularly, to a semiconductor apparatus with a plurality of individual stacked chips.
2. Related Art
A semiconductor apparatus is designed to operate at a high speed and to have a data storage area of a large capacity.
In order to meet such trends, a technology has been developed for producing a single product by stacking individual wafer chips and packaging them.
Generally, the stacked individual chips are assigned with addresses, and data are stored in the chips according to the assigned addresses.
To assign addresses to the stacked individual chips, the value of a code having a plurality of bits is sequentially increased or decreased.
Such technology for stacking individual chips and assigning to each individual chip as its address the value of a code sequentially increased or decreased is used on the assumption that none of the individual chips has failed.
In fact, if just one of the stacked individual chips fails, none of the stacked individual chips can be used. For example, if failure occurs in just one of the stacked individual chips in a semiconductor apparatus packaged with eight stacked layers, none of the remaining seven non-failed chips can be used. In this regard, the conventional art lacks efficiency and productivity.